一生一芯学习记录（E 阶段）（三） ​

接下来开始学习硬件描述语言Verilog，主要是记录一些语法内容和习题的答案。当然我们并不是将HDLBits上的习题全部做完，而是按照讲义内容去完成相应的习题，做昏头了，忘了有的习题不用做，主要是组合逻辑部分基本做完了，需要哪一部分自取就行。由于HDLBits是英文的，所以我会给出相应习题的中文解释。

E1 硬件描述语言 ​

这部分内容的索引按照讲义的内容和HDLBits上的顺序进行。每小节内容都有相应的标题对应。

Getting Started ​

Getting Started ​

习题：We’re going to start with a small bit of HDL to get familiar with the interface used by HDLBits. Here’s the description of the circuit you need to build for this exercise:

Build a circuit with no inputs and one output. That output should always drive 1 (or logic high).

搭建一个没有输入，只有一个输出的电路。且输出始终为1即高电平。

module top_module (output one)；

    assign one = 1'b1;

endmodule

Output Zero ​

习题：Build a circuit with no inputs and one output that outputs a constant 0.

搭建一个没有输入，只有一个输出的电路。且输出始终为0。

module top_module (output zero)；

    assign zero = 1'b0;

endmodule

Verilog Language ​

Basics ​

Simple wire ​

习题：Create a module with one input and one output that behaves like a wire.

搭建一个模块，具有一个输入和一个输出，并且这个模块表现出类似一根导线的形式。

和物理导线不同，Verilog中的导线或其他信号是方向性的，即信息只能从一个方向流向另一个方向，连续赋值将线右侧的值赋予左侧，且会实时变化。

模块的输入和输出端口同样也是有方向性的。

module top_module (input in, output out)；

    assign out = in;

endmodule

Four wires ​

习题：Create a module with 3 inputs and 4 outputs that behaves like wires that makes these connections:

a $\rightarrow$ w

b $\rightarrow$ x

b $\rightarrow$ y

c $\rightarrow$ z

搭建一个模块，具有三个输入和四个输出，输入输出的对应关系如下：

a $\rightarrow$ w

b $\rightarrow$ x

b $\rightarrow$ y

c $\rightarrow$ z

当使用assign进行连续赋值时，赋值的顺序对程序没有影响，本质上assign是表示电路的连接而不是数值的拷贝。

另外，正常情况下应该对导线进行额外的声明。因此assign是对已有导线的连接而不是创造导线。

module top_module(
    input a,b,c,
    output w,x,y,z
);

    assign w = a;
    assign x = b;
    assign y = b;
    assign z = c;

endmodule

Inverter ​

习题：Create a module that implements a NOT gate.

搭建一个具有非门功能的模块。

module top_module(input in, output out)；

    assign out = ~in;

endmodule

AND gate ​

习题：Create a module that implements an AND gate.

搭建一个具有与门功能的模块。

module top_module(
    input a, 
    input b, 
    output out
)；

    assign out = a & b;

endmodule

NOR gate ​

习题：Create a module that implements a NOR gate. A NOR gate is an OR gate with its output inverted. A NOR function needs two operators when written in Verilog.

搭建一个具有或非门功能的模块。或非门是对一个或门的输出取反。或非门用Verilog描述时需要两步。

module top_module(
    input a,
    input b,
    output out
);

    assign out = ~(a | b);

endmodule

XNOR gate ​

习题：Create a module that implements an XNOR gate.

搭建一个具有同或门功能的模块。

module top_module(
    input a,
    input b,
    output out
);

    assign out = ~(a ^ b);

endmodule

Declaring wires ​

当你需要使用导线时，需要在第一次使用之前在模块体内声明。在之后的学习中将会遇到更多类似的信号。

习题：Implement the following circuit. Create two intermediate wires (named anything you want) to connect the AND and OR gates together. Note that the wire that feeds the NOT gate is really wire out, so you do not necessarily need to declare a third wire here. Notice how wires are driven by exactly one source (output of a gate), but can feed multiple inputs.

If you’re following the circuit structure in the diagram, you should end up with four assign statements, as there are four signals that need a value assigned.

实现以下电路。搭建两根中间导线连接与门和或门。注意向非门供电的线是out，所以你不需要再声明第三根线。注意导线恰好由一个源驱动（即某个门的输出），但可以供电给多个输入端。

module top_module(
    input a,
    input b,
    input c,
    input d,
    output out,
    output out_n
);

    wire and_1;
    wire and_2;

    assign and_1 = a & b;
    assign and_2 = c & d;
    assign out = and_1 | and_2;
    assign out_n = ~out;

endmodule

7458 chip ​

习题：Create a module with the same functionality as the 7458 chip. It has 10 inputs and 2 outputs. You may choose to use an assign statement to drive each of the output wires, or you may choose to declare (four) wires for use as intermediate signals, where each internal wire is driven by the output of one of the AND gates. For extra practice, try it both ways.

搭建一个和7458芯片具有相同功能的模块。它有10个输入和2个输出。你可以选择直接利用assign去驱动每一个输出，或者也可以选择声明4根导线作为中继信号，每根中间线被一个与门的输出驱动。作为额外的练习，请你尝试这两种方式。

首先是直接驱动输出的写法。

module top_module(
    input p1a, p1b, p1c, p1d, p1e, p1f,
    output p1y,
    input p2a, p2b, p2c, p2d,
    output p2y
);

    assign p1y = (p1a & p1b & p1c) | (p1d & p1e & p1f);
    assign p2y = (p2a & p2b) | (p2c & p2d);

endmodule

接下来是利用中间导线的写法。

module top_module(
    input p1a, p1b, p1c, p1d, p1e, p1f,
    output p1y,
    input p2a, p2b, p2c, p2d,
    output p2y
);

    wire w1, w2, w3, w4;

    assign w1 = p1a & p1b & p1c;
    assign w2 = p1d & p1e & p1f;
    assign p1y = w1 | w2;

    assign w3 = p2a & p2b;
    assign w4 = p2c & p2d;
    assign p2y = w3 | w4;

endmodule

Vectors ​

Vectors ​

向量用于将相关的信号集合起来，更方便地进行操作。和C语言不同，声明向量的宽度需要在向量名之前。

习题：Build a circuit that has one 3-bit input, then outputs the same vector, and also splits it into three separate 1-bit outputs. Connect output o0 to the input vector’s position 0, o1 to position 1, etc.

搭建一个电路具有3位的输入，然后输出同样形式的向量，并且将输入分成3个1位的输出。连接输出o0和输入向量的位置0，o1和位置1，等等。

module top_module ( 
    input wire [2:0] vec,
    output wire [2:0] outv,
    output wire o2,
    output wire o1,
    output wire o0  
); 

    assign outv = vec;
    assign o0 = vec[0];
    assign o1 = vec[1];
    assign o2 = vec[2];

endmodule

Vectors in more detail ​

向量的声明格式如下：

类型 [最高位:最低位] 向量名

类型指定了向量的数据格式，通常是wire或reg。如果要声明输入和输出，也可以额外添加端口类型。

在Verilog中，一个向量一旦以某种端序被声明，就必须自始至终以同样的方式使用。

在Verilog中，线网类型的信号可以被一条assign语句隐式创建，也可以因为把某个未声明的标识符接到模块端口上而被隐式创建。隐式线网永远都是1位宽的wire，所以如果你本意是想用一个向量，它就会带来bug。

习题：Build a combinational circuit that splits an input half-word (16 bits, [15:0] ) into lower [7:0] and upper [15:8] bytes.

搭建一个组合电路，将输入的半字（16bits）分割成低8位和高8位。

module top_module( 
    input wire [15:0] in,
    output wire [7:0] out_hi,
    output wire [7:0] out_lo 
);

    assign out_hi = in[15:8];
    assign out_lo = in[7:0];

endmodule

Vector part select ​

习题：A 32-bit vector can be viewed as containing 4 bytes (bits [31:24], [23:16], etc.). Build a circuit that will reverse the byte ordering of the 4-byte word.

32位向量可以按照4个字节进行访问。搭建一个电路反转4个字节的顺序。

module top_module( 
    input [31:0] in,
    output [31:0] out 
);

    assign out[31:24] = in[7:0];
    assign out[23:16] = in[15:8];
    assign out[15:8] = in[23:16];
    assign out[7:0] = in[31:24];

endmodule

Bitwise operators ​

习题：Build a circuit that has two 3-bit inputs that computes the bitwise-OR of the two vectors, the logical-OR of the two vectors, and the inverse (NOT) of both vectors. Place the inverse of b in the upper half of out_not(i.e., bits [5:3]), and the inverse of a in the lower half.

搭建一个有两个3位输入的电路，电路用于计算两个向量的按位或，两个向量的逻辑或和两个向量取反。将b取反后放在out_not的高位，将a取反后放在低位。

module top_module( 
    input [2:0] a,
    input [2:0] b,
    output [2:0] out_or_bitwise,
    output out_or_logical,
    output [5:0] out_not
);

    assign out_or_bitwise = a | b;
    assign out_or_logical = a || b;
    assign out_not[2:0] = ~a;
    assign out_not[5:3] = ~b;

endmodule

Four-input gates ​

习题：Build a combinational circuit with four inputs,in[3:0].

There are 3 outputs:

• out_and: output of a 4-input AND gate.
• out_or: output of a 4-input OR gate.
• out_xor: output of a 4-input XOR gate.

搭建一个有4个输入的组合逻辑电路，用in[3:0]表示。

有3个输出：

• out_and：4输入与门的输出
• out_or：4输入或门的输出
• out_xor：4输入异或门的输出

module top_module( 
    input [3:0] in,
    output out_and,
    output out_or,
    output out_xor
);

    assign out_and = in[3] && in[2] && in[1] && in[0];
    assign out_or = in[3] || in[2] || in[1] || in[0];
    assign out_xor = in[3] ^ in[2] ^ in[1] ^ in[0];

endmodule

Vector concatenation operator ​

拼接操作符{a, b, c}用于将小的向量拼接成更大的向量。拼接时需要知道每个分量的宽度。拼接操作符可以用于连续赋值的左值和右值。

习题：Given several input vectors, concatenate them together then split them up into several output vectors. There are six 5-bit input vectors: a, b, c, d, e, and f, for a total of 30 bits of input. There are four 8-bit output vectors: w, x, y, and z, for 32 bits of output. The output should be a concatenation of the input vectors followed by two 1 bits。

给出一些输入向量，把它们拼接在一起然后分割成一些输出向量。有6个5位输入向量：a，b，c，d，e，f，总共30位的输入。有4个8位的输出向量：w，x，y，z，总共32位的输出。输出应该是输入向量的拼接和最后拼接的两个1。

module top_module (
    input [4:0] a, b, c, d, e, f,
    output [7:0] w, x, y, z 
);

    assign {w, x, y, z} = {a, b, c, d, e, f, 2'b11};

endmodule

Vector reversal 1 ​

习题：Given an 8-bit input vector [7:0], reverse its bit ordering.

给出一个8位的输入向量，逆转它的顺序。

module top_module( 
    input [7:0] in,
    output [7:0] out
);
    assign out = {in[0], in[1], in[2], in[3], in[4], in[5], in[6], in[7]};

endmodule

Replication operator ​

如果要将重复的向量拼接成一个更大的向量，采用上面的方法就显得过于冗长，因此，可以采用下面这种方式对重复的向量进行拼接。

{num{vector}}

习题：Build a circuit that sign-extends an 8-bit number to 32 bits. This requires a concatenation of 24 copies of the sign bit (i.e., replicate bit[7] 24 times) followed by the 8-bit number itself.

搭建一个电路用于将8位数字符号扩展到32位。这要求将8位数字的符号位扩展24次。

module top_module (
    input [7:0] in,
    output [31:0] out 
);

    assign out = { {24{in[7]}}, in };

endmodule

More replecation ​

习题：Given five 1-bit signals (a, b, c, d, and e), compute all 25 pairwise one-bit comparisons in the 25-bit output vector. The output should be 1 if the two bits being compared are equal.

给定五个1位向量，计算25对1位向量相比的结果。如果两个向量相等，那么输出应该是1。

module top_module (
    input a, b, c, d, e,
    output [24:0] out 
);
    
    assign out = ~( { {5{a}}, {5{b}}, {5{c}}, {5{d}}, {5{e}} } ^ {5{a, b, c, d, e}} );

endmodule

Modules: Hierarchy ​

Modules ​

将多个模块连接起来形成层级时，有两种方法，一种是根据位置，另一种是根据名字。根据位置连接类似于C语言调用函数的写法。根据名字调用则类似于下面这种写法。

verilog

mod_a instance2 ( .out(wc), .in1(wa), .in2(wb) );

习题：You may connect signals to the module by port name or port position. For extra practice, try both methods.

通过端口名字或端口位置连接信号和模块。作为额外练习，采用两种方式。

两种方法直接写在同一个顶层模块中：

module top_module ( input a, input b, output out );

    mod_a ( a, b, c );
    mod_a ( .in1(a), .in2(b), .out(out) );

endmodule

Connecting ports by position ​

习题：You are given a module named mod_a that has 2 outputs and 4 inputs, in that order. You must connect the 6 ports by position to your top-level module’s ports out1, out2, a, b, c, and d, in that order.

You are given the following module:

verilog

module mod_a ( output, output, input, input, input, input );

已经给出名为mod_a的模块，这个模块有2个输出和4个输入，顺序如下。你需要将6个接口按照位置连接到顶层模块的端口。

module top_module ( 
    input a, 
    input b, 
    input c,
    input d,
    output out1,
    output out2
);

    mod_a ( out1, out2, a, b, c, d );

endmodule

Connecting ports by name ​

习题：You are given a module named mod_a that has 2 outputs and 4 inputs, in some order. You must connect the 6 ports by name to your top-level module’s ports:

Port	Port in mod_a	Port in top_module
output	out1	out1
output	out2	out2
input	in1	a
input	in2	b
input	in3	c
input	in4	d

已经给出名为mod_a的模块，这个模块有2个输出和4个输入，顺序如下。你需要将6个接口按照名字连接到顶层模块的端口。

module top_module ( 
    input a, 
    input b, 
    input c,
    input d,
    output out1,
    output out2
);
	
    mod_a( .in1(a), .in2(b), .in3(c), .in4(d), .out1(out1), .out2(out2) );

endmodule

Three modules ​

习题：You are given a module my_dff with two inputs and one output (that implements a D flip-flop). Instantiate three of them, then chain them together to make a shift register of length 3. The clk port needs to be connected to all instances.

The module provided to you is: module my_dff ( input clk, input d, output q );

Note that to make the internal connections, you will need to declare some wires. Be careful about naming your wires and module instances: the names must be unique.

已经给出模块my_dff，有2个输入和1个输出。实例化3个这样的模块将它们连接起来形成一个长度为3的移位寄存器。clk接口需要连到所有的实体上。

在内部连线时可能会需要声明一些导线。注意导线和实例化的模块的名字必须是独一无二的。

module top_module ( input clk, input d, output q );

    wire q1, q2;
    my_dff d1 ( clk, d, q1 );
    my_dff d2 ( clk, q1, q2);
    my_dff d3 ( clk, q2, q);

endmodule

Modules and vectors ​

习题：You are given a module my_dff8 with two inputs and one output (that implements a set of 8 D flip-flops). Instantiate three of them, then chain them together to make a 8-bit wide shift register of length 3. In addition, create a 4-to-1 multiplexer (not provided) that chooses what to output depending on sel[1:0]: The value at the input d, after the first, after the second, or after the third D flip-flop. (Essentially, sel selects how many cycles to delay the input, from zero to three clock cycles.)

The module provided to you is: module my_dff8 ( input clk, input [7:0] d, output [7:0] q );

The multiplexer is not provided. One possible way to write one is inside an always block with a case statement inside.

给定一个模块my_dff8，它有2个输入和1个输出。实例化3个这样的模块，然后把它们连接起来形成一个8位的长度为3的移位寄存器。另外，搭建一个4选1多路选择器依靠sel[1:0]选择输出，选择的值分别是输入的d，第一个D触发器，第二个D触发器和第三个D触发器的输出。

module top_module ( 
    input clk, 
    input [7:0] d, 
    input [1:0] sel, 
    output [7:0] q 
);
    
    wire [7:0] q1, q2, q3;
    
    my_dff8 d1 ( clk, d, q1 );
    my_dff8 d2 ( clk, q1, q2);
    my_dff8 d3 ( clk, q2, q3);
    
    always @(*)begin
        case(sel)
            2'b11:q = q3;
            2'b10:q = q2;
            2'b01:q = q1;
            2'b00:q = d;
        endcase
    end
        
endmodule

Adder1 ​

习题：You are given a module add16 that performs a 16-bit addition. Instantiate two of them to create a 32-bit adder. One add16 module computes the lower 16 bits of the addition result, while the second add16 module computes the upper 16 bits of the result, after receiving the carry-out from the first adder. Your 32-bit adder does not need to handle carry-in (assume 0) or carry-out (ignored), but the internal modules need to in order to function correctly. (In other words, the add16 module performs 16-bit a + b + cin, while your module performs 32-bit a + b).

Connect the modules together as shown in the diagram below. The provided module add16 has the following declaration: module add16 ( input[15:0] a, input[15:0] b, input cin, output[15:0] sum, output cout );

给定模块add16是一个16位加法器。实例化2个这样的模块搭建一个32位加法器。一个16位加法器计算结果的低16位，另一个加法器在接受来自第一个加法器的进位后计算出结果的高16位。32位加法器不需要处理来自低位的进位和产生的高位的进位，但是内部逻辑要求正确。

module top_module(
    input [31:0] a,
    input [31:0] b,
    output [31:0] sum
);

	wire out1;
    add16 a1 ( a[15:0], b[15:0], 0, sum[15:0], out1 );
    add16 a2 ( a[31:16], b[31:16], out1, sum[31:16], );
    
endmodule

Adder2 ​

习题：In this exercise, you will create a circuit with two levels of hierarchy. Your top_module will instantiate two copies of add16 (provided), each of which will instantiate 16 copies of add1 (which you must write). Thus, you must write two modules: top_module and add1.

在这个练习中，你需要搭建一个2个层次的电路。你的top_module模块将会实例化2个add16（已提供），每个add16将会实例化16个add1（需要你完成）。

module top_module (
    input [31:0] a,
    input [31:0] b,
    output [31:0] sum
);

	wire out1;
    add16 a1 ( a[15:0], b[15:0], 0, sum[15:0], out1 );
    add16 a2 ( a[31:16], b[31:16], out1, sum[31:16], );
    
endmodule

module add1 ( input a, input b, input cin, output sum, output cout );

    assign sum = a ^ b ^ cin;
    assign cout = (a & b) | (b & cin) | (a & cin);

endmodule

Carry-select adder ​

习题：In this exercise, you are provided with the same module add16 as the previous exercise, which adds two 16-bit numbers with carry-in and produces a carry-out and 16-bit sum. You must instantiate three of these to build the carry-select adder, using your own 16-bit 2-to-1 multiplexer.

Connect the modules together as shown in the diagram below. The provided module add16 has the following declaration:

verilog

module add16 ( input[15:0] a, input[15:0] b, input cin, output[15:0] sum, output cout );

在这个练习中，提供了和之前练习相同的含有16位加法器，将2个16位数字相加求和得到16位数，并且包含进位输入和进位输出。你需要实例化3个这样的模块来搭建一个进位选择加法器，使用你自己的16位二选一多路选择器。

module top_module(
    input [31:0] a,
    input [31:0] b,
    output [31:0] sum
);
    
	wire cout;
    wire [15:0] a2sum;
    wire [15:0] a3sum;
    
    add16 a1 ( a[15:0], b[15:0], 0, sum[15:0], cout);
    add16 a2 ( a[31:16], b[31:16], 0, a2sum, );
    add16 a3 ( a[31:16], b[31:16], 1, a3sum, );
    
    multiplexer ( a2sum, a3sum, cout, sum[31:16] );
    
endmodule

module multiplexer (
    input [15:0] a,
    input [15:0] b,
    input sel,
    output reg [15:0] out
);
    
    always @(*)begin
        if(sel == 0)begin
            out = a;
        end
        else begin
            out = b;
        end
    end

endmodule

Adder-subtractor ​

习题：Build the adder-subtractor below.

You are provided with a 16-bit adder module, which you need to instantiate twice:

verilog

module add16 ( input[15:0] a, input[15:0] b, input cin, output[15:0] sum, output cout );

搭建下面的加减法器。

module top_module(
    input [31:0] a,
    input [31:0] b,
    input sub,
    output [31:0] sum
);
	wire cout;
    reg [31:0] bin;
    
    always @(*)begin
        if(sub == 1'b1)begin
            bin = b ^ {32{sub}};
        end
        else begin
            bin = b;
        end
    end
    
    add16 a1 ( a[15:0], bin[15:0], sub, sum[15:0], cout );
    add16 a2 ( a[31:16], bin[31:16], cout, sum[31:16], );
    
endmodule

Procedures ​

Always blocks (combinational) ​

在组合逻辑块中始终使用敏感列表(*)，为了防止漏掉信号。

在assign语句中左值必须是net类型的，比如wire；而在过程块中的赋值的左值必须是变量类型的，比如reg。

习题：Build an AND gate using both an assign statement and a combinational always block.

使用assign语句和组合逻辑块实现与门。

直接写在同一个module中。

module top_module(
    input a, 
    input b,
    output wire out_assign,
    output reg out_alwaysblock
);
    
	assign out_assign = a && b;
    
    always @(*)begin
        out_alwaysblock = a && b;
    end
    
endmodule

Always blocks (clocked) ​

Verilog中有3种赋值：

• 连续赋值(assign x = y)。只能用于过程块外面。
• 阻塞赋值(x = y)。只能用在过程块中。
• 非阻塞赋值(x <= y)。只能用在过程块中。

在组合逻辑块中，使用阻塞赋值；在时序逻辑块中，使用非阻塞赋值。

习题：Build an XOR gate three ways, using an assign statement, a combinational always block, and a clocked always block. Note that the clocked always block produces a different circuit from the other two: There is a flip-flop so the output is delayed.

用3种方法搭建一个异或门，即连续赋值，组合逻辑块和时序逻辑块。注意，由于时序逻辑块种有触发器，所以输出会有延迟，因此电路和其他两个不同。

module top_module(
    input clk,
    input a,
    input b,
    output wire out_assign,
    output reg out_always_comb,
    output reg out_always_ff   
);

    assign out_assign = a ^ b;
    
    always @(*)begin
        out_always_comb = a ^ b;
    end
    
    always @(posedge clk)begin
        out_always_ff = a ^ b;
    end
    
endmodule

If statement ​

习题：Build a 2-to-1 mux that chooses between a and b. Choose b if both sel_b1 and sel_b2 are true. Otherwise, choose a. Do the same twice, once using assign statements and once using a procedural if statement.

搭建一个二选一多路选择器。当sel_b1和sel_b2同时为真时选择b，否则选择a。完成两次，一次使用连续赋值，一次使用过程块。

module top_module(
    input a,
    input b,
    input sel_b1,
    input sel_b2,
    output wire out_assign,
    output reg out_always   
); 
	
    assign out_assign = (sel_b1 && sel_b2) ? b : a;
    
    always @(*)begin
        if(sel_b1 && sel_b2)begin
            out_always = b;
        end
        else begin
            out_always = a;
        end
    end
    
endmodule

If statement latchs ​

组合逻辑电路在任何情况下都需要给所有的输出指定一个值。这样才不会额外引入不必要的锁存器。

习题：The following code contains incorrect behaviour that creates a latch. Fix the bugs so that you will shut off the computer only if it’s really overheated, and stop driving if you’ve arrived at your destination or you need to refuel.

verilog

always @(*) begin
    if (cpu_overheated)
       shut_off_computer = 1;
end

always @(*) begin
    if (~arrived)
       keep_driving = ~gas_tank_empty;
end

下面的代码错误地产生了锁存器。修改这些bug，从而你可以只有在过热的时候关闭电脑；当你到达目的地时或者没有燃料时停止前进。

module top_module (
    input      cpu_overheated,
    output reg shut_off_computer,
    input      arrived,
    input      gas_tank_empty,
    output reg keep_driving  
); 

    always @(*) begin
        if (cpu_overheated)
           shut_off_computer = 1;
        else shut_off_computer = 0;
    end

    always @(*) begin
        if (~arrived)
           keep_driving = ~gas_tank_empty;
        else keep_driving = 0;
    end

endmodule

Case statement ​

习题：Case statements are more convenient than if statements if there are a large number of cases. So, in this exercise, create a 6-to-1 multiplexer. When sel is between 0 and 5, choose the corresponding data input. Otherwise, output 0. The data inputs and outputs are all 4 bits wide.

Be careful of inferring latches.

如果有大量的情况下，case语句比if语句更加方便。因此，在本练习中，搭建一个6选1多路选择器。当sel在0到5之间时，选择相对应的数据输出，否则输出0。输入数据和输出数据都是4位的。

module top_module ( 
    input [2:0] sel, 
    input [3:0] data0,
    input [3:0] data1,
    input [3:0] data2,
    input [3:0] data3,
    input [3:0] data4,
    input [3:0] data5,
    output reg [3:0] out   
);

    always@(*) begin
        case(sel)
            3'd0: out = data0;
            3'd1: out = data1;
            3'd2: out = data2;
            3'd3: out = data3;
            3'd4: out = data4;
            3'd5: out = data5;
            default: out = 0;
        endcase
    end

endmodule

Priority encoder ​

习题：Build a 4-bit priority encoder. For this problem, if none of the input bits are high (i.e., input is zero), output zero. Note that a 4-bit number has 16 possible combinations.

搭建一个4位优先编码器。在这个问题中，如果输入的数据中没有高电平，则输出是0.注意4位数有16中可能的组合。

module top_module (
    input [3:0] in,
    output reg [1:0] pos  
);	
    
    always @(*)begin
    	case(in)
      	  	4'd0: pos = 2'd0;
      	  	4'd1: pos = 2'd0;
      	  	4'd2: pos = 2'd1;
        	4'd3: pos = 2'd0;
        	4'd4: pos = 2'd2;
        	4'd5: pos = 2'd0;
        	4'd6: pos = 2'd1;
        	4'd7: pos = 2'd0;
        	4'd8: pos = 2'd3;
        	4'd9: pos = 2'd0;
        	4'd10: pos = 2'd1;
        	4'd11: pos = 2'd0;
        	4'd12: pos = 2'd2;
        	4'd13: pos = 2'd0;
        	4'd14: pos = 2'd1;
        	4'd15: pos = 2'd0;
    	endcase
    end
    
endmodule

Priority encoder with casez ​

习题：Build a priority encoder for 8-bit inputs. Given an 8-bit vector, the output should report the first (least significant) bit in the vector that is 1. Report zero if the input vector has no bits that are high.

搭建一个8位输入的优先编码器。指定一个8位向量，输出向量中最低位为1的位置。如果没有1，则输出0。

module top_module (
    input [7:0] in,
    output reg [2:0] pos 
);
	
    always @(*)begin
        casez(in)
            8'bzzzzzzz1: pos = 0;
            8'bzzzzzz10: pos = 1;
            8'bzzzzz100: pos = 2;
            8'bzzzz1000: pos = 3;
            8'bzzz10000: pos = 4;
            8'bzz100000: pos = 5;
            8'bz1000000: pos = 6;
            8'b10000000: pos = 7;
            default: pos = 0;
        endcase
    end
    
endmodule

Avoiding latches ​

习题：Suppose you’re building a circuit to process scancodes from a PS/2 keyboard for a game. Given the last two bytes of scancodes received, you need to indicate whether one of the arrow keys on the keyboard have been pressed. This involves a fairly simple mapping, which can be implemented as a case statement (or if-elseif) with four cases.

Scancode [15:0]	Arrow key
16’he06b	left arrow
16’he072	down arrow
16’he074	right arrow
16’he075	up arrow
Anything else	none

Your circuit has one 16-bit input, and four outputs. Build this circuit that recognizes these four scancodes and asserts the correct output.

假设你正在搭建一个电路从PS/2的键盘处理扫描码。给定收到的扫描码的最后两位，你需要指出是否有方向键被按下。这涉及一个简单的映射，用一个case语句即可实现。

你的电路有一个16位的输入和4个输出。搭建这个电路区分4个扫描码并且给出正确的输出。

为了避免创建锁存器，你可以给所有的输出一个默认的初始值。这样除了case引起输出的变化外，其他的输出保持这个初始值不变。

module top_module (
    input [15:0] scancode,
    output reg left,
    output reg down,
    output reg right,
    output reg up  
); 

    always @(*)begin
        left = 1'b0;
        down = 1'b0;
        right = 1'b0;
        up = 1'b0;
        
        case(scancode)
            16'he06b: left = 1'b1;
            16'he072: down = 1'b1;
            16'he074: right = 1'b1;
            16'he075: up = 1'b1;
        endcase
    end
              
endmodule

More Verilog Features ​

Conditional ternary operator ​

习题：Given four unsigned numbers, find the minimum. Unsigned numbers can be compared with standard comparison operators (a < b). Use the conditional operator to make two-way min circuits, then compose a few of them to create a 4-way min circuit. You’ll probably want some wire vectors for the intermediate results.

给出4个无符号数，找到最小值。无符号数可以用标准比较运算符进行比较。用条件运算符去搭建两路最小电路。然后用它们搭建4路最小电路。你可能会需要一些线向量作为中间结果。

module top_module (
    input [7:0] a, b, c, d,
    output [7:0] min
);
    
    wire [7:0] min1;
    wire [7:0] min2;
    
    assign min1 = ( ( a < b ) ? a : b );
    assign min2 = ( ( min1 < c ) ? min1 : c );
    assign min = ( ( min2 < d ) ? min2 : d );
    
endmodule

Reduction operator ​

缩减运算符可以对向量中每个bit进行与，或和异或的操作。

这些操作符是一元操作符，你也可以将它们的输出反转，搭建成与非，或非和同或的门。

习题：Parity checking is often used as a simple method of detecting errors when transmitting data through an imperfect channel. Create a circuit that will compute a parity bit for a 8-bit byte (which will add a 9th bit to the byte). We will use "even" parity, where the parity bit is just the XOR of all 8 data bits.

奇偶校验经常被用来作为在不可靠的信道中传输数据时用来发现错误的简单方法。搭建一个用来计算一个8位数据的奇偶校验码的电路。我们将会用偶校验，即全部8个bit的异或。

module top_module (
    input [7:0] in,
    output parity
);
    
    assign parity = ^ in[7:0];

endmodule

Reduction: Even wider gates ​

习题：Build a combinational circuit with 100 inputs, in[99:0].

There are 3 outputs:

• out_and: output of a 100-input AND gate.
• out_or: output of a 100-input OR gate.
• out_xor: output of a 100-input XOR gate.

搭建一个有100个输入的组合电路。

有3个输出：

• 100个输入的与门的输出。
• 100个输入的或门的输出。
• 100个输入的异或门的输出。

module top_module( 
    input [99:0] in,
    output out_and,
    output out_or,
    output out_xor 
);
	
    assign out_and = & in;
    assign out_or = | in;
    assign out_xor = ^ in;
    
endmodule

Combinational for-loop: Vector reversal 2 ​

习题：Given a 100-bit input vector [99:0], reverse its bit ordering.

给出一个100bit的输入向量，调转每个bit的顺序。

module top_module (
	input [99:0] in,
	output reg [99:0] out
);
	
	always @(*)begin
		int i;
        for (i = 0; i < 100; i = i + 1)
            out[i] = in[99-i];
    end
	
endmodule

在本题的官方答案中使用了一个函数$bits()，这个函数可以返回一个信号的宽度。

Combinational for-loop: 255-bit population count ​

习题：A "population count" circuit counts the number of '1’s in an input vector. Build a population count circuit for a 255-bit input vector.

人口计数电路统计一个输入向量中有多少个1。搭建一个255位输入向量的人口计数电路。

module top_module( 
    input [254:0] in,
    output [7:0] out 
);
	
    always @(*)begin
        int i;
        out = 1'b0;
        for (i = 0; i < 255; i = i + 1)
            if (in[i])
                out = out + 1'b1;
    end
    
endmodule

Generate for-loop: 100-bit binary adder 2 ​

习题：Create a 100-bit binary ripple-carry adder by instantiating 100 full adders.

通过实例化100个全加器，搭建一个100位二进制行波进位加法器。

module top_module( 
    input [99:0] a, b,
    input cin,
    output [99:0] cout,
    output [99:0] sum 
);
    
    full_adder (a[0], b[0], cin, cout[0], sum[0]);
    genvar i;
    generate
        for(i = 1; i < 100; i = i + 1) begin : adder
            full_adder (a[i], b[i], cout[i-1], cout[i], sum[i]);
        end
    endgenerate
    
endmodule

module full_adder(
    input a,
    input b,
    input cin,
    output cout,
    output sum
);
    
    assign sum = a ^ b ^ cin;
    assign cout = (a & b) | (b & cin) | (a & cin);
    
endmodule

这个程序如果出现报错的话，大概率出现在for循环那一行，实际上是由于含声明的生成块必须具名。

Generate for-loop : 100-digit BCD adder ​

习题：You are provided with a BCD one-digit adder named bcd_fadd that adds two BCD digits and carry-in, and produces a sum and carry-out.

Instantiate 100 copies of bcd_fadd to create a 100-digit BCD ripple-carry adder. Your adder should add two 100-digit BCD numbers (packed into 400-bit vectors) and a carry-in to produce a 100-digit sum and carry out.

已经提供给你了一个1个十进制数的BCD加法器，它将两个BCD数字和进位相加，然后产生一个求和值和进位。

实例化100个加法器搭建一个100个十进制数BCD的行波进位加法器。你的加法器应该将两个100十进制的BCD数字和进位相加得到100个十进制数的求和值和进位输出。

module top_module( 
    input [399:0] a, b,
    input cin,
    output cout,
    output [399:0] sum 
);

    wire [99:0] cout_temp;
    
    bcd_fadd (a[3:0], b[3:0], cin, cout_temp[0], sum[3:0]);
    
    genvar i;
    generate
        for(i = 4; i < 400; i = i + 4) begin : bcd
            bcd_fadd (a[(i+3):i], b[(i+3):i], cout_temp[i/4-1], cout_temp[i/4], sum[(i+3):i]);
        end
    endgenerate
    
    assign cout = cout_temp[99];
    
endmodule

Circuits ​

Combinational Logic ​

Basic Gates ​

Wire ​

习题：Implement the following circuit:

搭建以下电路

module top_module (
    input in,
    output out
);

    assign out = in;

endmodule

GND ​

习题：Implement the following circuit:

搭建以下电路

module top_module (
    output out
);
    
    assign out = 1'b0;

endmodule

NOR ​

习题：Implement the following circuit:

搭建以下电路

module top_module (
    input in1,
    input in2,
    output out
);
	
    assign out = ~(in1 | in2);
    
endmodule

Another gate ​

习题：Implement the following circuit:

搭建以下电路

module top_module (
    input in1,
    input in2,
    output out
);
    
    assign out = in1 & (~in2);

endmodule

Two gates ​

习题：Implement the following circuit:

搭建以下电路

module top_module (
    input in1,
    input in2,
    input in3,
    output out
);
    
    assign out = (~(in1 ^ in2)) ^ in3;

endmodule

More logic gates ​

习题：Ok, let’s try building several logic gates at the same time. Build a combinational circuit with two inputs, a and b.

There are 7 outputs, each with a logic gate driving it:

• out_and: a and b
• out_or: a or b
• out_xor: a xor b
• out_nand: a nand b
• out_nor: a nor b
• out_xnor: a xnor b
• out_anotb: a and-not b

接下来一次性搭建多个逻辑门。搭建一个组合逻辑电路，有两个输入，7个输出，包括与、或、异或、与非、或非、同或等。最后这个是a与~b。

module top_module( 
    input a, b,
    output out_and,
    output out_or,
    output out_xor,
    output out_nand,
    output out_nor,
    output out_xnor,
    output out_anotb
);

    assign out_and = a & b;
    assign out_or = a | b;
    assign out_xor = a ^ b;
    assign out_nand = ~(a & b);
    assign out_nor = ~(a | b);
    assign out_xnor = ~(a ^ b);
    assign out_anotb = a & (~b);
    
endmodule

7420 chip ​

习题：The 7400-series integrated circuits are a series of digital chips with a few gates each. The 7420 is a chip with two 4-input NAND gates.

Create a module with the same functionality as the 7420 chip. It has 8 inputs and 2 outputs.

7400系列集成电路是一系列有若干门电路的数字芯片。7420有2个4输入与非门。

搭建一个与7420芯片有相同功能的电路，它有8个输入和2个输出。

module top_module ( 
    input p1a, p1b, p1c, p1d,
    output p1y,
    input p2a, p2b, p2c, p2d,
    output p2y 
);

    assign p1y = ~(p1a & p1b & p1c & p1d);
    assign p2y = ~(p2a & p2b & p2c & p2d);
    
endmodule

Truth tables ​

习题：

Row number	Inputs x3 x2 x1	Outputs f
0	0 0 0	0
1	0 0 1	0
2	0 1 0	1
3	0 1 1	1
4	1 0 0	0
5	1 0 1	1
6	1 1 0	0
7	1 1 1	1

Create a combinational circuit that implements the above truth table.

搭建一个组合逻辑电路，符合上面的真值表。

module top_module( 
    input x3,
    input x2,
    input x1,
    output f
);
	
    assign f = (x1 & x3) | (x2 & (~x3));
    
endmodule

Two-bit equality ​

习题：Create a circuit that has two 2-bit inputs A[1:0] and B[1:0], and produces an output z. The value of z should be 1 if A = B, otherwise z should be 0.

搭建一个电路有两个输入和一个输出。当输入相等时输出为1，否则为0。

module top_module ( input [1:0] A, input [1:0] B, output z ); 

    assign z = (A == B);
    
endmodule

Simple circuit A ​

习题：Module A is supposed to implement the function z = (x^y) & x. Implement this module.

模块A实现了z = (x^y) & x这个逻辑式，实现这个模块。

module top_module (input x, input y, output z);

    assign z = (x ^ y) & x;
    
endmodule

Simple circuit B ​

习题：Circuit B can be described by the following simulation waveform:

Implement this circuit.

电路B可以描述成下面的仿真波形图，实现这个电路。

很容易的看出电路B是同或电路。

module top_module ( input x, input y, output z );
	
    assign z = ~(x ^ y);
    
endmodule

Combine circuits A and B ​

习题：The top-level design consists of two instantiations each of subcircuits A and B, as shown below.

Implement this circuit.

顶层模块由实例化两个子模块A和B组成，如图所示。实现这个电路。

module top_module (input x, input y, output z);
	
    wire z1, z2, z3, z4;
    module_a a1 (x, y, z1);
    module_b b1 (x, y, z2);
    module_a a2 (x, y, z3);
    module_b b2 (x, y, z4);
    assign z = (z1 | z2) ^ (z3 & z4);
    
endmodule

module module_a (input x, input y, output z);

    assign z = (x ^ y) & x;
    
endmodule

module module_b ( input x, input y, output z );
	
    assign z = ~(x ^ y);
    
endmodule

Ring or vibrate? ​

习题：Suppose you are designing a circuit to control a cellphone’s ringer and vibration motor. Whenever the phone needs to ring from an incoming call (input ring), your circuit must either turn on the ringer (output ringer = 1) or the motor (output motor = 1), but not both. If the phone is in vibrate mode (input vibrate_mode = 1), turn on the motor. Otherwise, turn on the ringer.

假设你正在设计一个电路控制电话铃声和震动马达。每当来电话需要响铃的时候，你的电路必须响铃或者马达震动，但是不能同时进行。如果电话处于震动模式，就打开马达。否则响铃。

module top_module (
    input ring,
    input vibrate_mode,
    output ringer,
    output motor
);

    assign ringer = ring & (~vibrate_mode);
    assign motor = ring & vibrate_mode;
    
endmodule

Thermostat ​

习题：A heating/cooling thermostat controls both a heater (during winter) and an air conditioner (during summer). Implement a circuit that will turn on and off the heater, air conditioning, and blower fan as appropriate.

The thermostat can be in one of two modes: heating (mode = 1) and cooling (mode = 0). In heating mode, turn the heater on when it is too cold (too_cold = 1) but do not use the air conditioner. In cooling mode, turn the air conditioner on when it is too hot (too_hot = 1), but do not turn on the heater. When the heater or air conditioner are on, also turn on the fan to circulate the air. In addition, the user can also request the fan to turn on (fan_on = 1), even if the heater and air conditioner are off.

Try to use only assign statements, to see whether you can translate a problem description into a collection of logic gates.

一个冷热恒温器控制一个加热器和一个空调，实现一个电路可以打开和关闭加热器以及空调，并且在合适的时候打开风扇。

恒温器处于两个模式之一：加热模式和制冷模式。在加热模式下，当特别冷的时候打开加热器并且不使用空调。在制冷模式下，当特别热的时候打开空调并且不使用加热器。当加热器或空调打开的时候，同时打开风扇循环空气。此外，即使加热器和空调都是关闭的，用户也可以要求打开风扇。

尝试只用assign语句，看看你如何将一个问题描述成一系列逻辑门。

module top_module (
    input too_cold,
    input too_hot,
    input mode,
    input fan_on,
    output heater,
    output aircon,
    output fan
); 
	
    assign heater = mode & too_cold;
    assign aircon = (~mode) & too_hot;
    assign fan = heater | aircon | fan_on;
        
endmodule

3-bit population count ​

习题：A "population count" circuit counts the number of '1’s in an input vector. Build a population count circuit for a 3-bit input vector.

人口计数电路计算一个输入向量中1的个数。搭建一个输入向量是3位的人口计数电路。

module top_module( 
    input [2:0] in,
    output [1:0] out 
);
    
    always @(*) begin
        int i;
        out = 0;
        for (i = 0; i < 3; i = i + 1) begin
            out = out + in[i];
        end
    end

endmodule

Gates and vectors ​

习题：You are given a four-bit input vector in[3:0]. We want to know some relationships between each bit and its neighbour:

• out_both: Each bit of this output vector should indicate whether both the corresponding input bit and its neighbour to the left (higher index) are '1'. For example, out_both[2] should indicate if in[2] and in[3] are both 1. Since in[3] has no neighbour to the left, the answer is obvious so we don’t need to know out_both[3].
• out_any: Each bit of this output vector should indicate whether any of the corresponding input bit and its neighbour to the right are '1'. For example, out_any[2] should indicate if either in[2] or in[1] are 1. Since in[0] has no neighbour to the right, the answer is obvious so we don’t need to know out_any[0].
• out_different: Each bit of this output vector should indicate whether the corresponding input bit is different from its neighbour to the left. For example, out_different[2] should indicate if in[2] is different from in[3]. For this part, treat the vector as wrapping around, so in[3]'s neighbour to the left is in[0].

给定4位的输入向量。我们想知道每个bit和它邻近的bit之间的关系。

• out_both：输出向量的每个bit应当表明与之相对应的输入bit和它左边的bit是不是都为1。例如，out_both[2]应该表明in[2]和in[3]是不是同为1。因为in[3]左侧没有bit，因此我们不需要out_both[3]。
• out_any：输出向量的每个bit应当表明与之相对应的输入bit和它右边的bit是不是至少有一个1。例如，out_any[2]应该表明in[2]或in[1]是不是为1。因为in[0]右侧没有bit，因此我们不需要out_any[0]。
• out_different：输出向量的每个bit应当表面与之相对应的输入bit和它左边的bit是不是不同。例如，out_different[2]应当表明in[2]是否与in[3]不同。在这一部分中，我们认为向量是环状的，因此in[3]的左侧是in[0]。

module top_module( 
    input [3:0] in,
    output [2:0] out_both,
    output [3:1] out_any,
    output [3:0] out_different 
);
    
    assign out_both = in[2:0] & in[3:1];
    assign out_any = in[3:1] | in[2:0];
    assign out_different = in ^ {in[0], in[3:1]};

endmodule

Even longer vectors ​

习题：You are given a 100-bit input vector in[99:0]. We want to know some relationships between each bit and its neighbour:

• out_both: Each bit of this output vector should indicate whether both the corresponding input bit and its neighbour to the left are '1'. For example, out_both[98] should indicate if in[98] and in[99] are both 1. Since in[99] has no neighbour to the left, the answer is obvious so we don’t need to know out_both[99].
• out_any: Each bit of this output vector should indicate whether any of the corresponding input bit and its neighbour to the right are '1'. For example, out_any[2] should indicate if either in[2] or in[1] are 1. Since in[0] has no neighbour to the right, the answer is obvious so we don’t need to know out_any[0].
• out_different: Each bit of this output vector should indicate whether the corresponding input bit is different from its neighbour to the left. For example, out_different[98] should indicate if in[98] is different from in[99]. For this part, treat the vector as wrapping around, so in[99]'s neighbour to the left is in[0].

给定100位的输入向量。我们想知道每个bit和它邻近的bit之间的关系。

• out_both：输出向量的每个bit应当表明与之相对应的输入bit和它左边的bit是不是都为1。例如，out_both[98]应该表明in[98]和in[99]是不是同为1。因为in[99]左侧没有bit，因此我们不需要out_both[3]。
• out_any：输出向量的每个bit应当表明与之相对应的输入bit和它右边的bit是不是至少有一个1。例如，out_any[2]应该表明in[2]或in[1]是不是为1。因为in[0]右侧没有bit，因此我们不需要out_any[0]。
• out_different：输出向量的每个bit应当表面与之相对应的输入bit和它左边的bit是不是不同。例如，out_different[98]应当表明in[98]是否与in[99]不同。在这一部分中，我们认为向量是环状的，因此in[99]的左侧是in[0]。

module top_module( 
    input [99:0] in,
    output [98:0] out_both,
    output [99:1] out_any,
    output [99:0] out_different 
);
    
    assign out_both = in[98:0] & in[99:1];
    assign out_any = in[99:1] | in[98:0];
    assign out_different = in ^ {in[0], in[99:1]};

endmodule

Multiplexers ​

2-to-1 multiplexer ​

习题：Create a one-bit wide, 2-to-1 multiplexer. When sel=0, choose a. When sel=1, choose b.

搭建一个1位的二选一多路选择器。当sel=0时选a，当sel=1时选b。

module top_module( 
    input a, b, sel,
    output out 
);
    
    assign out = sel ? b : a;

endmodule

2-to-1 bus multiplexer ​

习题：Create a 100-bit wide, 2-to-1 multiplexer. When sel=0, choose a. When sel=1, choose b.

搭建一个100位的二选一多路选择器。当sel=0时选a，当sel=1时选b。

module top_module( 
    input [99:0] a, b,
    input sel,
    output [99:0] out 
);
    
    assign out = sel ? b : a;
	
endmodule

9-to-1 multiplexer ​

习题：Create a 16-bit wide, 9-to-1 multiplexer. sel=0 chooses a, sel=1 chooses b, etc. For the unused cases (sel=9 to 15), set all output bits to '1'.

搭建一个16位的9选1多路选择器。当sel=0时选a，当sel=1时选b，以此类推。对于没有用的情况，将所有输出置1。

module top_module( 
    input [15:0] a, b, c, d, e, f, g, h, i,
    input [3:0] sel,
    output [15:0] out 
);
    
    always @(*) begin
        case (sel)
            4'd0: out = a;
            4'd1: out = b;
            4'd2: out = c;
            4'd3: out = d;
            4'd4: out = e;
            4'd5: out = f;
            4'd6: out = g;
            4'd7: out = h;
            4'd8: out = i;
            default: out = {16{1'b1}};
        endcase
    end

endmodule

256-to-1 multiplexer ​

习题：Create a 1-bit wide, 256-to-1 multiplexer. The 256 inputs are all packed into a single 256-bit input vector. sel=0 should select in[0], sel=1 selects bits in[1], sel=2 selects bits in[2], etc.

搭建一个1位的256选1多路选择器。256个输入被打包进1个256位输入向量。当sel=0时选in[0]，当sel=1时选in[1]，当sel=2时选in[2]，以此类推。

module top_module( 
    input [255:0] in,
    input [7:0] sel,
    output out 
);
	
    assign out = in[sel];
    
endmodule

256-to-1 4-bit multiplexer ​

习题：Create a 4-bit wide, 256-to-1 multiplexer. The 256 4-bit inputs are all packed into a single 1024-bit input vector. sel=0 should select bits in[3:0], sel=1 selects bits in[7:4], sel=2 selects bits in[11:8], etc.

搭建一个4位的256选1多路选择器。这256个4位的输入被打包进1个1024位的输入向量。当sel=0时选in[3:0]，当sel=1时选in[7:4]，当sel=2时选in[11:8]，以此类推。

module top_module( 
    input [1023:0] in,
    input [7:0] sel,
    output [3:0] out 
);
	
    assign out[0] = in[sel * 4];
    assign out[1] = in[sel * 4 + 1];
    assign out[2] = in[sel * 4 + 2];
    assign out[3] = in[sel * 4 + 3];
        
endmodule

这个题需要注意的是，位选的索引可以是一个变量，但是部分选取时端点必须是一个常数。

Arithmetic Circuits ​

Half adder ​

习题：Create a half adder. A half adder adds two bits (with no carry-in) and produces a sum and carry-out.

搭建一个半加器。半加器将两个bit相加（没有进位输入），产生一个求和值和一个进位输出。

module top_module( 
    input a, b,
    output cout, sum 
);

    assign cout = a & b;
    assign sum = a ^ b;
    
endmodule

Full adder ​

习题：Create a full adder. A full adder adds three bits (including carry-in) and produces a sum and carry-out.

搭建一个全加器。一个全加器将3个bit（包括进位输入）相加，产生一个求和值和一个进位输出。

module top_module( 
    input a, b, cin,
    output cout, sum 
);
    
	assign sum = a ^ b ^ cin;
    assign cout = (a & b) | (b & cin) | (a & cin);
    
endmodule

3-bit binary adder ​

习题：Now that you know how to build a full adder, make 3 instances of it to create a 3-bit binary ripple-carry adder.

现在你知道如何搭建一个全加器了，实例化3个全加器搭建一个3位的行波进位加法器。

module top_module( 
    input [2:0] a, b,
    input cin,
    output [2:0] cout,
    output [2:0] sum 
);
	
    full_adder adder1 (a[0], b[0], cin, cout[0], sum[0]);
    full_adder adder2 (a[1], b[1], cout[0], cout[1], sum[1]);
    full_adder adder3 (a[2], b[2], cout[1], cout[2], sum[2]);
    
endmodule

module full_adder(
    input a, b,
    input cin,
    output cout,
    output sum
);
    
    assign sum = a ^ b ^ cin;
    assign cout = (a & b) | (b & cin) | (a & cin);
    
endmodule

Adder ​

习题：Implement the following circuit:

实现下面的电路。

module top_module (
    input [3:0] x,
    input [3:0] y, 
    output [4:0] sum
);

    assign sum = x + y;
    
endmodule

Signed addition overflow ​

习题：Assume that you have two 8-bit 2’s complement numbers, a[7:0] and b[7:0]. These numbers are added to produce s[7:0]. Also compute whether a (signed) overflow has occurred.

假设你有两个8位补码。这些数字相加得到结果。同时需要计算是否发生了符号溢出。

module top_module (
    input [7:0] a,
    input [7:0] b,
    output [7:0] s,
    output overflow
); 
 
    assign s = a + b;
    assign overflow = (~a[7] & ~b[7] & s[7]) | (a[7] & b[7] & ~s[7]);

endmodule

100-bit binary adder ​

习题：Create a 100-bit binary adder. The adder adds two 100-bit numbers and a carry-in to produce a 100-bit sum and carry out.

搭建一个100位二进制加法器。加法器将两个100位二进制数和进位输入相加产生一个100位的求和值和进位输出。

module top_module( 
    input [99:0] a, b,
    input cin,
    output cout,
    output [99:0] sum 
);
    
    assign {cout, sum} = a + b + cin;
    
endmodule

Sequential Logic ​

Latches and Flip-Flops ​

D flip-flop ​

习题：Create a single D flip-flop.

搭建一个D触发器。

module top_module (
    input clk,    
    input d,
    output reg q 
);

    always @(posedge clk) begin
        q <= d;
    end

endmodule

DFF with reset value ​

习题：Create 8 D flip-flops with active high synchronous reset. The flip-flops must be reset to 0x34 rather than zero. All DFFs should be triggered by the negative edge of clk.

搭建8个带有主动高电平同步复位的D触发器。触发器必须复位到0x34而不是0。所有的触发器都是时钟下降沿触发。

module top_module (
    input clk,
    input reset,
    input [7:0] d,
    output [7:0] q
);
	
    always @(negedge clk) begin
        if(reset)q <= 7'h34;
        else q <= d;
    end
    
endmodule

DFF with asynchronous reset ​

习题：Create 8 D flip-flops with active high asynchronous reset. All DFFs should be triggered by the positive edge of clk.

搭建8个具有主动高电平异步复位的D触发器。所有的触发器都在时钟信号的高电平触发。

module top_module (
    input clk,
    input areset,
    input [7:0] d,
    output [7:0] q
);
	
    always @(posedge clk or posedge areset) begin
        if(areset)q <= 8'b0;
        else q <= d;
    end
    
endmodule

DFF with byte enable ​

习题：Create 16 D flip-flops. It’s sometimes useful to only modify parts of a group of flip-flops. The byte-enable inputs control whether each byte of the 16 registers should be written to on that cycle. byteena[1] controls the upper byte d[15:8], while byteena[0] controls the lower byte d[7:0].

resetn is a synchronous, active-low reset.

All DFFs should be triggered by the positive edge of clk.

搭建16个D触发器。有的时候修改一群触发器的一部分是有用的，字节使能输入控制16个寄存器中每个字节在当前周期是否应该写入。byteena[1]控制高字节，byteena[0]控制低字节。

resetn是主动低电平同步复位信号。

所有的触发器都在时钟的上升沿触发。

module top_module (
    input clk,
    input resetn,
    input [1:0] byteena,
    input [15:0] d,
    output [15:0] q
);
	
    always @(posedge clk) begin
        if(!resetn)q <= 0;
        else begin
            if(byteena[1])q[15:8] <= d[15:8];
            if(byteena[0])q[7:0] <= d[7:0];
        end
    end
    
endmodule

Mux and DFF ​

习题：Consider the sequential circuit below:

Assume that you want to implement hierarchical Verilog code for this circuit, using three instantiations of a submodule that has a flip-flop and multiplexer in it. Write a Verilog module (containing one flip-flop and multiplexer) named top_module for this submodule.

考虑下面这个时序逻辑电路：

假设你想要分层实现这个电路，通过实例化3个子模块，每个子模块包括一个触发器和一个多路选择器。请为这个子模块写一个Verilog模块。

module top_module (
	input clk,
	input L,
	input r_in,
	input q_in,
	output reg Q
);
    wire d;
    
    assign d = L ? r_in : q_in;
    
    always @(posedge clk) begin
        Q <= d;
    end

endmodule

Create circiut from truth table ​

习题：A JK flip-flop has the below truth table.Implement a JK flip-flop with only a D-type flip-flop and gates. Note: Qold is the output of the D flip-flop before the positive clock edge.

J	K	Q
0	0	Qold
0	1	0
1	0	1
1	1	~Qold

JK触发器有以下的真值表。实现JK触发器只需要D触发器和逻辑门。注意：Qold是D触发器在时钟上升沿之前的输出。

module top_module (
    input clk,
    input j,
    input k,
    output Q
); 
    
    always @(posedge clk) begin
        case({j,k})
            2'b00: Q <= Q;
            2'b01: Q <= 0;
            2'b10: Q <= 1;
            2'b11: Q <= ~Q;
        endcase
    end
        
endmodule

Detect an edge ​

习题：For each bit in an 8-bit vector, detect when the input signal changes from 0 in one clock cycle to 1 the next (similar to positive edge detection). The output bit should be set the cycle after a 0 to 1 transition occurs.

对于一个8位向量的每个bit，检查输入信号是否从某一个时钟周期的0，变成下一个时钟周期的1（类似于上升沿检测）。在0到1的跳变发生之后的那个时钟周期，对应的输出位应当被置位。

module top_module (
    input clk,
    input [7:0] in,
    output [7:0] pedge
);
	
    reg [7:0] temp;
    
    always @(posedge clk) begin
        temp <= in;
        pedge = in & ~temp;
    end
    
endmodule

Detect both edges ​

习题：For each bit in an 8-bit vector, detect when the input signal changes from one clock cycle to the next (detect any edge). The output bit should be set the cycle after a 0 to 1 transition occurs.

对于一个8位向量的每个bit，检查输入信号是否从某一个时钟周期的 到下一个时钟周期发生变化（任意边沿检测）。在0到1的跳变发生之后的那个时钟周期，对应的输出位应当被置位。

module top_module (
    input clk,
    input [7:0] in,
    output [7:0] anyedge
);
	reg [7:0] temp;
    
    always @(posedge clk) begin
        temp <= in;
        anyedge = in ^ temp;
    end

endmodule

Edge capture register ​

习题：For each bit in a 32-bit vector, capture when the input signal changes from 1 in one clock cycle to 0 the next. "Capture" means that the output will remain 1 until the register is reset (synchronous reset).

Each output bit behaves like a SR flip-flop: The output bit should be set (to 1) the cycle after a 1 to 0 transition occurs. The output bit should be reset (to 0) at the positive clock edge when reset is high. If both of the above events occur at the same time, reset has precedence.

对于32位向量的每个bit，当输入信号在当前时钟周期为1，下一时钟周期为0时捕获它。捕获的意思是输出将会一直保持1，直到寄存器被复位。

每个输出bit的行为都像一个SR触发器：在从1到0跳变之后的周期输出bit应该被置1。当复位信号为高时，在时钟上升沿输出bit应该被复位到0。如果两件事情同时发生，则复位的优先级更高。

module top_module (
    input clk,
    input reset,
    input [31:0] in,
    output [31:0] out
);
    
    reg [31:0] temp;
    
    always @(posedge clk) begin
        temp <= in;
        if(reset)out <= 0;
        else out = (temp & ~in) | out;
    end
    
endmodule

Dual-edge triggered flip-flop ​

习题：Build a circuit that functionally behaves like a dual-edge triggered flip-flop.

搭建一个双边沿触发的触发器。

这个题比较麻烦，首先先给出一种能跑过仿真的答案，但是实际上在之前F阶段学习数字电路的时候就提到过时钟信号不能作为组合电路的输入或输出。

module top_module (
    input clk,
    input d,
    output q
);

    reg q1,q2;
    always @(posedge clk) begin
        q1 <= d;
    end
    always @(negedge clk) begin
        q2 <= d;
    end
    
    assign q = clk ? q1 : q2;
    
endmodule

当然，HDLbits也给出了答案。比较巧妙的利用了异或门。

module top_module(
	input clk,
	input d,
	output q);
	
	reg p, n;
	
    always @(posedge clk)
        p <= d ^ n;
        
    always @(negedge clk)
        n <= d ^ p;

    assign q = p ^ n;
      
endmodule

Counters ​

Decade counter again ​

习题：Make a decade counter that counts 1 through 10, inclusive. The reset input is synchronous, and should reset the counter to 1.

做一个十进制计数器，从1数到10。复位信号是同步的，将计数器复位到1。

module top_module (
    input clk,
    input reset,
    output [3:0] q
);
    
    always @(posedge clk)begin
        if(reset | (q == 10))q <= 1;
        else q <= q + 1;
    end

endmodule

Slow decade counter ​

习题：Build a decade counter that counts from 0 through 9, inclusive, with a period of 10. The reset input is synchronous, and should reset the counter to 0. We want to be able to pause the counter rather than always incrementing every clock cycle, so the slowena input indicates when the counter should increment.

搭建一个十进制计数器，从0数到9，周期是10。复位输入是同步的，并且将计数器复位到0。我们想要能够暂停计数而不是每个时钟周期都增加，所以slowena输入表明了什么时候计数器应该增加。

module top_module (
    input clk,
    input slowena,
    input reset,
    output [3:0] q
);
    
    always @(posedge clk) begin
        if(reset)q <= 0;
        else if((q == 9) & slowena)q <= 0;
        else if(slowena) q <= q + 1;
    end
    
endmodule

Counter 1000 ​

习题：From a 1000 Hz clock, derive a 1 Hz signal, called OneHertz, that could be used to drive an Enable signal for a set of hour/minute/second counters to create a digital wall clock. Since we want the clock to count once per second, the OneHertz signal must be asserted for exactly one cycle each second. Build the frequency divider using modulo-10 (BCD) counters and as few other gates as possible. Also output the enable signals from each of the BCD counters you use (c_enable[0] for the fastest counter, c_enable[2] for the slowest).

The following BCD counter is provided for you. Enable must be high for the counter to run. Reset is synchronous and set high to force the counter to zero. All counters in your circuit must directly use the same 1000 Hz signal.

从一个 1000 Hz 的时钟出发，派生出一个 1 Hz 的信号，命名为 OneHertz，它可以用来驱动一组时/分/秒计数器的使能信号，从而构成一个数字挂钟。由于我们希望时钟每秒计数一次，OneHertz 信号必须在每一秒中恰好被置位一个时钟周期。请使用模 10（BCD）计数器来构建这个分频器，并尽可能少地使用其它门电路。此外，还要输出你所使用的每一个 BCD 计数器的使能信号（c_enable[0] 对应最快的那个计数器，c_enable[2] 对应最慢的）。

下面这个 BCD 计数器已经为你提供。Enable 必须为高，计数器才会运行。Reset 是同步复位，置高会强制计数器清零。你电路中的所有计数器都必须直接使用同一个 1000 Hz 信号。

module top_module (
    input clk,
    input reset,
    output OneHertz,
    output [2:0] c_enable
); 

    wire [3:0] q0,q1,q2;
    
    bcdcount counter0 (clk, reset, c_enable[0], q0);
    bcdcount counter1 (clk, reset, c_enable[1], q1);
    bcdcount counter2 (clk, reset, c_enable[2], q2);
    
    assign c_enable[1] = (q0 == 9);
    assign c_enable[2] = (q0 == 9 & q1 == 9);
    assign OneHertz = (q0 == 9 & q1 == 9 & q2 == 9);
    
    always @(posedge clk) begin
        c_enable[0] <= 1;
    end

endmodule

12-hour clock ​

习题：Create a set of counters suitable for use as a 12-hour clock (with am/pm indicator). Your counters are clocked by a fast-running clk, with a pulse on ena whenever your clock should increment (i.e., once per second).

reset resets the clock to 12:00 AM. pm is 0 for AM and 1 for PM. hh, mm, and ss are two BCD (Binary-Coded Decimal) digits each for hours (01-12), minutes (00-59), and seconds (00-59). Reset has higher priority than enable, and can occur even when not enabled.

搭建一系列计数器用于12小时时钟。你的计数器由快速运行的clk计时，当你的时钟需要增加的时候有一个ena的脉冲。

reset在中午12点时复位。上午pm为0，下午为1。hh，mm和ss是两个BCD数字分别表示时，分，秒。复位信号比使能信号有更高的优先级，而且即使没有使能也可以复位。

module top_module(
    input clk,
    input reset,
    input ena,
    output pm,
    output [7:0] hh,
    output [7:0] mm,
    output [7:0] ss
); 
    
    always @(posedge clk) begin
        if(reset)begin
            hh <= 8'h12;
            mm <= 0;
            ss <= 0;
            pm <= 0;
        end
        else begin
            if(ena) begin
                ss <= ss + 1;
                if(ss[3:0] == 9) begin
                    ss[3:0] <= 0;
                    ss[7:4] <= ss[7:4] + 1;
                end
                if(ss == 8'h59) begin
                    mm <= mm + 1;
                    if(mm[3:0] == 9) begin
                    	mm[3:0] <= 0;
                        mm[7:4] <= mm[7:4] + 1;
                	end
                    ss <= 0;
                end
                if(ss == 8'h59 & mm == 8'h59) begin
                    hh <= hh + 1;
                    if(hh[3:0] == 9) begin
                    	hh[3:0] <= 0;
                        hh[7:4] <= hh[7:4] + 1;
                	end
                    mm <= 0;
                end
                if(hh == 8'h11 & ss == 8'h59 & mm == 8'h59) begin
                    pm <= ~pm;
                end
                if(hh == 8'h12 & ss == 8'h59 & mm == 8'h59) begin
            		hh <= 8'h01;
                end
            end
        end
    end
                      
endmodule

Shift Registers ​

Left/right rotator ​

习题：Build a 100-bit left/right rotator, with synchronous load and left/right enable. A rotator shifts-in the shifted-out bit from the other end of the register, unlike a shifter that discards the shifted-out bit and shifts in a zero. If enabled, a rotator rotates the bits around and does not modify/discard them.

• load: Loads shift register with data[99:0] instead of rotating.
• ena[1:0]: Chooses whether and which direction to rotate.
  • 2’b01 rotates right by one bit
  • 2’b10 rotates left by one bit
  • 2’b00 and 2’b11 do not rotate.
• q: The contents of the rotator.

搭建一个100位左右旋转器，具有同步装载和左右使能。旋转器从寄存器的另一端将移出bit移入寄存器，不像移位寄存器之间丢弃移出bit并且移入0。如果使能，旋转器旋转bit而不是修改或丢弃。

module top_module(
    input clk,
    input load,
    input [1:0] ena,
    input [99:0] data,
    output reg [99:0] q
); 
    
    always @(posedge clk) begin
        if(load)q <= data;
        else if(ena == 2'b01)q <= {q[0], q[99:1]};
        else if(ena == 2'b10)q <= {q[98:0], q[99]};
    end
    
endmodule

Left/right arithmetic shift by 1 or 8 ​

习题：Build a 64-bit arithmetic shift register, with synchronous load. The shifter can shift both left and right, and by 1 or 8 bit positions, selected by amount.

An arithmetic right shift shifts in the sign bit of the number in the shift register (q[63] in this case) instead of zero as done by a logical right shift. Another way of thinking about an arithmetic right shift is that it assumes the number being shifted is signed and preserves the sign, so that arithmetic right shift divides a signed number by a power of two.

There is no difference between logical and arithmetic left shifts.

• load: Loads shift register with data[63:0] instead of shifting.
• ena: Chooses whether to shift.
• amount: Chooses which direction and how much to shift.
  • 2’b00: shift left by 1 bit.
  • 2’b01: shift left by 8 bits.
  • 2’b10: shift right by 1 bit.
  • 2’b11: shift right by 8 bits.
• q: The contents of the shifter.

搭建一个有同步加载的64位算术移位寄存器。这个移位器可以左移或者右移，移位可以移1位或8位，通过amount选择。

算术移位寄存器右移时移动的是符号位而不是像逻辑移位寄存器移0。另一种理解算术移位的方式是假设被移动的数据是有符号数，保留符号位，因此算术右移相当于有符号数除以2的幂。

逻辑左移和算术左移没有区别。

module top_module(
    input clk,
    input load,
    input ena,
    input [1:0] amount,
    input [63:0] data,
    output reg [63:0] q
); 

    always @(posedge clk) begin
        if(load)q <= data;
        else if(ena)begin
            case(amount)
                2'b00: q <= {q[62:0], 1'b0};
                2'b01: q <= {q[55:0], 8'b0};
                2'b10: q <= {q[63], q[63:1]};
                2'b11: q <= {{8{q[63]}}, q[63:8]};
            endcase
        end
    end
    
endmodule

5-bits LFSR ​

习题：A linear feedback shift register is a shift register usually with a few XOR gates to produce the next state of the shift register. A Galois LFSR is one particular arrangement where bit positions with a "tap" are XORed with the output bit to produce its next value, while bit positions without a tap shift. If the taps positions are carefully chosen, the LFSR can be made to be "maximum-length". A maximum-length LFSR of n bits cycles through $2^n-1$ states before repeating (the all-zero state is never reached).

The following diagram shows a 5-bit maximal-length Galois LFSR with taps at bit positions 5 and 3. (Tap positions are usually numbered starting from 1). Note that I drew the XOR gate at position 5 for consistency, but one of the XOR gate inputs is 0.

Build this LFSR. The reset should reset the LFSR to 1.

线性反馈移位寄存器是一种移位寄存器，通常带有若干异或门，用来产生移位寄存器的下一个状态。Galois LFSR是其中一种特定的连接方式：带抽头的bit位与输出bit异或产生下一个值。不带抽头的bit位直接移位。如果抽头位置仔细选择，LSFR可以做成最大长度的。一个n位的最大长度的LFSR在重复之前会经历 $2^n-1$ 个状态（全部为0的状态不会出现）

下面的图展示了5位最大长度Galois LFSR，抽头位于第5位和第3位（抽头位置通常从1开始）。注意我在第5位也画了异或门，但一个输入为0。

搭建这个LFSR。reset应该把LFSR复位为1。

module top_module(
    input clk,
    input reset,
    output [4:0] q
); 
	
    always @(posedge clk) begin
        if(reset)q <= 5'h1;
            else q <= {(q[0] ^ 0), q[4], (q[3] ^ q[0]), q[2], q[1]};
    end
    
endmodule

Shift register ​

习题：Implement the following circuit:

搭建下面的电路。

module top_module (
    input clk,
    input resetn,
    input in,
    output out
);

    wire [3:0] q;
    
    always @(posedge clk) begin
        if(!resetn)q = 0;
        else q <= {in, q[3:1]};
    end
    
    assign out = q[0];
    
endmodule

3-input LUT ​

习题：In this question, you will design a circuit for an 8x1 memory, where writing to the memory is accomplished by shifting-in bits, and reading is "random access", as in a typical RAM. You will then use the circuit to realize a 3-input logic function.

First, create an 8-bit shift register with 8 D-type flip-flops. Label the flip-flop outputs from Q[0]…Q[7]. The shift register input should be called S, which feeds the input of Q[0] (MSB is shifted in first). The enable input controls whether to shift. Then, extend the circuit to have 3 additional inputs A,B,C and an output Z. The circuit’s behaviour should be as follows: when ABC is 000, Z=Q[0], when ABC is 001, Z=Q[1], and so on. Your circuit should contain ONLY the 8-bit shift register, and multiplexers. (Aside: this circuit is called a 3-input look-up-table (LUT)).

在这个习题中，你将会设计一个 $8 \times 1$ 存储器的电路，通过移位写u存储，读取则是随机访问，与典型RAM一样。你将会使用这个电路去实现一个3输入逻辑电路。

首先，用8个D触发器搭建一个8位的移位寄存器。将触发器的输出命名为Q[0]…Q[7]。移位寄存器的输入命名为S，馈入Q[0]的输入端（最高有效位先移入）。使能端控制是否移位。然后扩展电路增加3个输入端A，B，C和1个输出Z.电路的行为应该如下：当ABC=000时，Z=Q[0]；当ABC=001时，Z=Q[1]，以此类推。你的电路应该只包括8位移位寄存器和多路复用器。（这个电路称为3输入LUT）。

module top_module (
    input clk,
    input enable,
    input S,
    input A, B, C,
    output Z 
); 
    
    wire [7:0] Q;
    
    always @(posedge clk) begin
        if(enable)Q <= {Q[6:0], S};
    end
    
    assign Z = Q[{A, B, C}];
    
endmodule

More Circuits ​

Rule 90 ​

习题：Rule 90 is a one-dimensional cellular automaton with interesting properties.

The rules are simple. There is a one-dimensional array of cells (on or off). At each time step, the next state of each cell is the XOR of the cell’s two current neighbours. A more verbose way of expressing this rule is the following table, where a cell’s next state is a function of itself and its two neighbours:

Left	Center	Right	Center’s next state
1	1	1	0
1	1	0	1
1	0	1	0
1	0	0	1
0	1	1	1
0	1	0	0
0	0	1	1
0	0	0	0

In this circuit, create a 512-cell system (q[511:0]), and advance by one time step each clock cycle. The load input indicates the state of the system should be loaded with data[511:0]. Assume the boundaries (q[-1] and q[512]) are both zero (off).

Rule 90是一个具有有趣性质的一维元胞自动机。

规则很简单。有一个一维的细胞数组，在每一个时间步，每个细胞的下一个状态是它两个邻居的异或。下面这张表用更啰嗦的方式描述了这条规则。

在这个电路中，搭建一个512个细胞的系统，并且每个时钟周期前进一个时间步。load输入指定将data[511:0]加载入系统。假设边界（q[-1]和q[512]）都是0。

module top_module(
    input clk,
    input load,
    input [511:0] data,
    output [511:0] q 
); 
	
    always @(posedge clk) begin
        if(load)q <= data;
        else begin
            q <= {1'b0, q[511:1]} ^ {q[510:0], 1'b0};
        end
    end
    
endmodule

Rule 110 ​

习题：Rule 110 is a one-dimensional cellular automaton with interesting properties.

There is a one-dimensional array of cells (on or off). At each time step, the state of each cell changes. In Rule 110, the next state of each cell depends only on itself and its two neighbours, according to the following table:

Left	Center	Right	Center’s next state
1	1	1	0
1	1	0	1
1	0	1	1
1	0	0	0
0	1	1	1
0	1	0	1
0	0	1	1
0	0	0	0

In this circuit, create a 512-cell system (q[511:0]), and advance by one time step each clock cycle. The load input indicates the state of the system should be loaded with data[511:0]. Assume the boundaries (q[-1] and q[512]) are both zero (off).

Rule 110是一个具有有趣性质的一维元胞自动机。

有一个一维的细胞数组。在每一个时间步，每个细胞的状态都发生变化。在Rule 110中，每个细胞的下一个状态只依赖于它自身和它的两个相邻的细胞，依据下表。

在这个电路中，搭建一个512个细胞的系统，并且每个时钟周期前进一个时间步。load输入指定将data[511:0]加载入系统。假设边界（q[-1]和q[512]）都是0。

module top_module(
    input clk,
    input load,
    input [511:0] data,
    output [511:0] q
); 
	
    always @(posedge clk) begin
        if(load)q <= data;
        else q <= (q & ~{1'b0, q[511:1]}) | (q ^ {q[510:0], 1'b0});
    end
    
endmodule

Conway’s Game of Life 16 $\times$ 16 ​

习题：Conway’s Game of Life is a two-dimensional cellular automaton.

The "game" is played on a two-dimensional grid of cells, where each cell is either 1 (alive) or 0 (dead). At each time step, each cell changes state depending on how many neighbours it has:

• 0-1 neighbour: Cell becomes 0.
• 2 neighbours: Cell state does not change.
• 3 neighbours: Cell becomes 1.
• 4+ neighbours: Cell becomes 0.

The game is formulated for an infinite grid. In this circuit, we will use a 16x16 grid. To make things more interesting, we will use a 16x16 toroid, where the sides wrap around to the other side of the grid. For example, the corner cell (0,0) has 8 neighbours: (15,1), (15,0), (15,15), (0,1), (0,15), (1,1), (1,0), and (1,15). The $16 \times 16$ grid is represented by a length 256 vector, where each row of 16 cells is represented by a sub-vector: q[15:0] is row 0, q[31:16] is row 1, etc. (This tool accepts SystemVerilog, so you may use 2D vectors if you wish.)

• load: Loads data into q at the next clock edge, for loading initial state.
• q: The $16 \times 16$ current state of the game, updated every clock cycle.

The game state should advance by one timestep every clock cycle.

Conway’s Game of Life是一个二维的元胞自动机。

这个游戏在一个二维网格上进行，每个元胞要么是1要么是0。每一个时间步，每个元胞根据周围元胞的数量改变状态。

• 0-1个邻居：元胞变为0。
• 2个邻居：元胞保持不变。
• 3个邻居：元胞变为1。
• 4+个邻居：元胞变为0。

该游戏原本制定在无限网格上。在这个电路中，我们使用 $16 \times 16$ 的网格。为了让问题更有意思，我们将采用 $16 \times 16$ 的环状网格，即各边会绕回到网格的另一侧，例如，角落处的元胞 (0,0) 有8个邻居：(15,1)、(15,0)、(15,15)、(0,1)、(0,15)、(1,1)、(1,0) 和 (1,15)。这个 $16 \times 16$ 的网格用一个长度为256的向量表示。每一行的16个元胞由一个子向量表示，q[15:0]为第0行，q[31:16]为第1行，依此类推。

• load：在下一个时钟沿将data加载到q，进行初始化。
• q：这个游戏当前的$16 \times 16$状态，每个时钟周期更新。

每个周期游戏状态前进一个时间步。

module top_module(
    input clk,
    input load,
    input [255:0] data,
    output [255:0] q 
);
    
    reg [255:0] q_up;
    reg [255:0] q_down;
    reg [255:0] q_left;
    reg [255:0] q_right;
    reg [255:0] q_leftup;
    reg [255:0] q_rightup;
    reg [255:0] q_leftdown;
    reg [255:0] q_rightdown;
    
    int up,down;
    
    always @(*) begin
        int i;
        for(i = 0; i < 256; i = i + 1) begin
            up = (i-16+256)%256;
            down = (i+16)%256;
            
            q_up[i] = q[up];
            q_down[i] = q[down];
            q_left[i] = q[(i%16 == 0) ? i+15 : i-1];
            q_right[i] = q[(i%16 == 15) ? i-15 : i+1];
            q_leftup[i] = q[(up%16 == 0) ? up+15 : up-1];
            q_leftdown[i] = q[(down%16 == 0) ? down+15 : down-1];
            q_rightup[i] = q[(up%16 == 15) ? up-15 : up+1];
            q_rightdown[i] = q[(down%16 == 15) ? down-15 : down+1];
        end
    end
       
    always @(posedge clk) begin
        if(load)q <= data;
        else begin
            int i;
            for(i = 0; i < 256; i = i + 1) begin
                case(q_up[i] + q_down[i] + q_left[i] + q_right[i]
                     + q_leftup[i] + q_rightup[i] + q_leftdown[i] + q_rightdown[i])
                    3'd2: q[i] <= q[i];
                    3'd3: q[i] <= 1;
                    default: q[i] <= 0;
                endcase
            end
        end
    end
                
endmodule